The present invention relates generally to integrated circuits, such as microprocessors, and more particularly to a system and method for optimizing performance of integrated circuits by dynamically manipulating the clock of such integrated circuits to account for events such as power disturbances, therein.
Typically, an integrated circuit (or xe2x80x9cchipxe2x80x9d) utilizes a clock to control the circuits therein. As is well known in the art, chips are commonly designed such that their circuits operate synchronously according to a clock signal. That is, the exact times at which any output of the circuits can change states are determined by a clock signal. The clock signal is generally a rectangular pulse train or square wave signal input to or generated within the chip. While some chips (or portions thereof) may operate asynchronously, such asynchronous components are generally more difficult to design and troubleshoot than are synchronous components. For instance, synchronous components are generally easier to troubleshoot because the circuit outputs can change only at specific instants of time. In other words, such components of the chip are synchronized to the clock-signal transitions (also known as xe2x80x9cclocksxe2x80x9d) of the chip.
Because operation of the chip""s circuits are triggered upon clock-signal transitions, xe2x80x9ceventsxe2x80x9d (or xe2x80x9cpower disturbancesxe2x80x9d) are often encountered upon the occurrence of particular clock-signal transitions. That is, as a chip""s circuits operate they draw power, and upon a clock-signal transition occurring many of the circuits may draw additional power to perform the tasks triggered by such clock-signal transition. As a result, clock-signal transitions often result in voltage transients within the chip. Because the operation of the chip""s circuits is triggered by clock-signal transitions, much of the circuits"" operation is congregated at the clock-signal transitions. Therefore, power disturbances are commonly encountered upon clock-signal transitions. For instance, the power drawn by the circuits may be relatively flat (constant) until the occurrence of a particular clock-signal transition in which many of the circuits are triggered, thereby causing an increase in the power drawn by such circuits.
For example, upon the leading edge of a clock-signal transition, a program counter (e.g., a register) may be incremented. Additionally, at some point the program counter will flip all of its bits (which may, for example, be 256 bits or more) over from all ones to its beginning point of all zeros, which may cause the output of many gates within the chip to change states (e.g., change from an output of 1 to an output of 0). Such operation of many gates being triggered upon the occurrence of the clock-signal transition will typically result in a power disturbance (e.g., a very high voltage transient) within the chip. Of course, many other situations may be encountered in which a clock-signal transition may trigger operation of circuitry within the chip resulting in a power disturbance.
Additionally, certain clock-signal transitions result in higher voltage transients than other clock-signal transitions. For instance, in the above example of a program counter, the clock-signal transition in which all of the program counter""s bits change their state results in a much higher voltage transient than a clock-signal transition in which only one or two of the program counter""s bits change their state. Of course, the clock-signal transition resulting in the program counter changing the state of all of its bits occurs only on a relatively small percentage of the clock-signal transitions (e.g., only once out of every 65 thousand clock-signal transitions).
Thus, depending on the operations triggered within the chip on each clock-signal transition, certain clock-signal transitions result in a much greater power disturbance than others. As still another example, suppose that on 60 percent of the clock-signal transitions within a chip a 100 millivolt (mV) drop in voltage occurs within the chip, on 30 percent of the clock-signal transitions a 150 mV drop in voltage occurs within the chip, and on 10 percent of the clock-signal transitions, a 200 mV drop in voltage occurs within the chip. Prior art chips are generally implemented to operate at a frequency suitable for the absolute worst case power disturbance that may be encountered to prevent the chip from failing upon the occurrence of such worst case power disturbance. That is, during development of a chip it is typically tested with some code sequence designed to cause the absolute worst case power disturbance in the chip""s performance, and from such testing a suitable clock frequency for the chip is determined that enables the chip to operate even upon the occurrence of such worst case power disturbance.
For instance, in the above example, the chip""s clock signal would be implemented at a sufficiently low frequency such that the chip does not fail upon the occurrence of a 200 mV drop in voltage. That is, prior art chips are commonly designed having additional voltage margin implemented therein such that the chips are capable of performing even when the chips"" operation result in voltage transients within the chips. However, the worst case power disturbance may only be encountered on a very small percentage of the clock-signal transitions (e.g., on only 10 percent of the clock-signal transitions in the above example). Thus, prior art chip designs sacrifice chip performance during those clock-signal transitions that do not trigger such worst case power disturbance (e.g., during 90 percent of the clock-signal transitions in the above example) in order to prevent failure of the chip during the clock-signal transitions that do trigger such worst case power disturbance. Of course, such a sacrifice has been deemed much more desirable in chips of the prior art than an implementation which results in failure of the chip during the worst case power disturbances. Accordingly, performance of prior art chips has been limited by the implementation of a static clock signal set at a frequency sufficiently low to enable the chip to operate during the worst case power disturbances.
The present invention is directed to a system and method which enable dynamic manipulation of a clock signal within an integrated circuit to enable optimum performance of the integrated circuit. That is, a desire exists for a system and method which enable a clock signal to be manipulated within an integrated circuit to allow for optimum performance of the chip depending on events, such as power disturbances, being (or about to be) encountered by the chip. As used herein, xe2x80x9ceventsxe2x80x9d include any situations that result in or lead to a disturbance within the integrated unit. xe2x80x9cDisturbancexe2x80x9d is intended to be used broadly to encompass any type of disturbance within an integrated circuit, including without limitation power disturbance and operational disturbance (e.g., incorrect performance or failure of the integrated circuit).
The present invention is directed to a system and method which provide an integrated circuit having a clock signal which it can dynamically manipulate in response to detected events. In a preferred embodiment, the integrated circuit includes synchronous circuitry that receives and operates according to a clock signal. The integrated circuit of a preferred embodiment further includes event detection circuitry that is arranged to monitor the operation of the integrated circuit and detect an event therein. Additionally, clock manipulator circuitry is included in the integrated circuit of a preferred embodiment to manipulate the clock signal, responsive to the event detection circuitry detecting an event, to enable the integrated circuit to cope with the detected event without failing.
In response to an event being detected, the clock manipulator circuitry may be implemented to manipulate the clock signal in various manners, such as by altering the duty cycle of the clock signal, delaying the occurrence of a transition of the clock signal, or altering the frequency of the clock signal, as examples. The event detection circuitry of a preferred embodiment may further detect the end of an event, and may notify the clock manipulator circuitry to manipulate the clock signal to the optimum clock signal for normal operation of the integrated circuit. In one embodiment, the event detection circuitry includes trigger circuitry operable to detect an anticipated operation of the integrated circuit known to trigger an event that leads to a disturbance, such as a power disturbance, within the integrated circuit. For example, the trigger circuitry may monitor the operation of the chip for particular data (or sequences of data), commands, addresses, control signals and/or instructions, as examples, which are known to commonly trigger disturbances, such as power disturbances, within the chip. For instance, software code may be programmed within the trigger circuitry to enable such trigger circuitry to detect/predict such events that lead to disturbances. As one example, the trigger circuitry may monitor the operation of the chip to determine when the program counter is about to flip all of its bits from its highest value to its starting point, and may notify the clock manipulator circuitry of this xe2x80x9ceventxe2x80x9d to enable the clock manipulator circuitry to manipulate the clock signal such that the chip can effectively cope with the resulting power disturbance.
It should be recognized that as used herein, xe2x80x9cdetecting an eventxe2x80x9d is intended to encompass predicting the event based on the detection of an operation of the integrated circuit known to trigger a disturbance within the chip. That is, some implementations may enable detection of an event prior to the event actually occurring. In this manner, detection of operations of the integrated circuit that foreshadow the actual occurrence of an event may enable early detection (prediction) of such event. Particularly regarding the above-described trigger circuitry that is capable of detecting anticipated events, such trigger circuitry may be implemented to detect operations of the integrated circuit (e.g., addresses, data sequences, instructions, control signals, etcetera) that typically lead to (or foreshadow) an event, thereby enabling the trigger circuitry to predict the occurrence of an event (thus detecting such event). By detecting an event early based on foreshadowing operations of the chip, the chip may timely respond to such event to enable the chip to cope with the event.
In another embodiment, the event detection circuitry includes a sensor for sensing a particular condition within the chip indicating an event. As one example, the event detection circuitry may include a sensor operable to detect voltage transients (e.g., beyond some threshold amount) within the chip which indicate an event. As another example, a temperature sensor may detect an event, such as the temperature being beyond the temperature range for the integrated circuit""s operation, and in response to the temperature sensor detecting a temperature beyond the suitable range, the trigger circuitry may manipulate the clock in an attempt to enable the integrated circuit to cope with such event (e.g., by slowing the clock to allow the integrated circuit to cool. In this manner, the event detection circuitry may detect unanticipated events occurring within the chip""s operation.
In a preferred embodiment, the chip is implemented with event detection circuitry that comprises both trigger circuitry for detecting anticipated events and sensor circuitry for detecting unanticipated events. Thus, in a preferred embodiment, if either the trigger circuitry or the sensor circuitry detect an event, then the clock manipulator circuitry may, in response thereto, adjust (or manipulate) the chip""s clock signal to enable the chip to effectively cope with such event.
Accordingly, a preferred embodiment of the present invention enables both anticipated and unanticipated events to be detected, and in response, the chip""s clock may be manipulated to effectively compensate for such event to prevent the chip from failing. Because the various embodiments of the present invention enable the chip""s clock to be dynamically manipulated upon detection of an event, the chip may be implemented to operate very efficiently. For example, rather than implementing a sufficiently slow clock frequency to allow enough margin for the absolute worst case event that may be incurred (as is commonly done in prior art chips), a very high frequency may be implemented at which the chip""s clock may operate until detection of an event, at which time the chip""s clock may be manipulated (e.g., by adjusting the clock""s duty cycle or adjusting the clock""s frequency) to enable the chip to cope with the detected event. Therefore, the chip""s performance is not sacrificed during those periods when an event is not occurring, and the chip""s operation also does not fail upon the occurrence of an event. Thus, dynamically adjusting the chip""s clock in accordance with detected events within the chip enable optimum performance from the chip.